We are designing a waveform digitizer for the MuLan experiment at
BNL. MuLan is a precision measurement of the lifetime of the positive
muon. The experimental cycle is very simple. Every 20 usec, 10-20
surface muons (24-28 MeV/c) muons are sent into a very thin target.
Once they are stopped, we start our clock and look for signals from
decay positrons in the two layer scintillator detector which surrounds
the stopping target. The signals are generally MIPs from the positrons
whose energies range from 0 up to 53 MeV. There are 180 elements in the
detector, each of two layers, or 360 channels in all, whose signals will
be sampled at 500 MHz. The main reason for using the WFD approach is 
pileup, when two pulses look like one, which we would like to minimize.
In the case of g-2, our deadtime is about 3 ns and the smaller the deadtime
the smaller the corresponding correction.
     The main difference between the MuLan and g-2 is the nature of the
beam. In g-2, there is a roughly 2 second rest period between data cycles,
during which the whole detector can be read out. In Mulan, we have a continuous
beam and would like to be able to take data and read it out at the same time.
We are also more sensitive to backgrounds. For example, a muon which
arrives after the clock has started distorts the exponential shape
of the time spectrum. Our artificial pulsed beam will minimize  stray 
muons but, all the same, we will monitor the entrance to the detector with
a thin but highly efficient counter to veto the event should such an 
unwanted visitor intrude. This means that the data should be fill coherent so
that we can veto the data from that event and no other.
      The time of each pulse can be reconstructed from the waveform record 
without much trouble but the zero time also needs to be established. One
approach would be to load t0 pulse times into every channel, which is 
essentially what we do on g-2. However, this incurs the overhead of
adding a great number of superfluous bytes into the data stream. In contrast
to g-2, most channels will be empty on a given cycle. An alternative is to
record each t0 in a separate channel and, in the online processing, subtract
out the appropriate time offset from each channel's time counter.
       The data structure in the WFD should include a number of 
flash ADC samples plus a time word. With a 2 ns time tick, 16 bits corresponds
to 131 usec or about six cycles. 20 bits is close to 2 ms, 32 bits about 8
seconds. In any case, sparse data readout will be required. The event builder/
pulse fitter processors should have access to the t0s for each channel which
could be a force digitization pulse at the beginning of each data
segment. With those times for each channel and the time of each cycle in
a separate clock, we can unambiguously specify the time of each pulse.
       



label each piece of data by cycle and 


Minimum sampling : 8 bit, 500 ns
zero suppression: digital or analog trigger
timing stabilty: 2 ps stability, early to late 
amplitude stability: .05% stability,early to late  early to late 
       means over 20 usec.
cycling time of experiment: 20 usec
occupancy per channel  < 10%  (<20 e+ into 200 channels)
400 channels, 200 channel pairs - if one channel is written to 
     memory, the other is written to memory also (should be able to turn
     off tihs feature)
Sparse readout, cycles should be read out together
typical signal ~ 125 PEs, sampled for 50 ns
total rate for experiment: ~ 60 Mbytes/sec
continuous readout required - read out while reading in
features: write to real memory, instead of FIFO
	  external clock input
	  force write to memory (no zero suppress)
          external start (or latch start) input, stop also
          memory test option
          threshold, gain, offset controls
	  fast interface to online processing
	  inhibit input
6U or 9U VME

Time schedule: want prototype ready in 1 year, production in 2 years